Design and Simulation of 32-Point FFT Using Mixed Radix Algorithm for FPGA Implementation

This paper focus on the development of the fast Fourier transform (FFT), based on Decimation-In-Time (DIT) domain by using Mixed-Radix algorithm (Radix-4 and Radix-8).Fast Fourier transforms, popularly known as FFTs, have become an integral part of any type of digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters such as area, time delay, power and speed. In this paper a comparison of area and minimum time delay are drawn between the proposed design of 32 point FFT by using Mixed-Radix algorithmwithRadix-2 algorithm. Here our goal is to implement Mixed Radix 32-point FFT by using hardware language (VHDL). Simulation and synthesis of design is done using Xilinx ISE 14.7. The result shows significant reduction in terms of area complexity and minimum time delay.